As the value and use of information continues to increase, individuals and businesses seek additional ways to process and store information. One option available to users is information handling systems. An information handling system generally processes, compiles, stores, and/or communicates information or data for business, personal, or other purposes thereby allowing users to take advantage of the value of the information. Because technology and information handling needs and requirements vary between different users or applications, information handling systems may also vary regarding what information is handled, how the information is handled, how much information is processed, stored, or communicated, and how quickly and efficiently the information may be processed, stored, or communicated. The variations in information handling systems allow for information handling systems to be general or configured for a specific user or specific use such as financial transaction processing, airline reservations, enterprise data storage, or global communications. In addition, information handling systems may include a variety of hardware and software components that may be configured to process, store, and communicate information and may include one or more computer systems, data storage systems, and networking systems.
An information handling system may include one or more power supply units (PSUs) for providing electrical energy to components of the information handling system. Typically, a power supply unit (PSU) is configured to operate from an input alternating current (AC) source of electrical energy, which the PSU converts to a direct current (DC) output. Thus, typically a PSU may include a rectifier and/or power factor correction stage to receive the input AC source and rectify the input AC waveform to charge a bulk capacitor to a desired voltage. A direct-current-to-direct-current (DC-DC) stage may convert the voltage on the bulk capacitor to a DC output voltage which may be used to power components of the information handling system. Other PSUs may be powered from a DC input source (e.g., a 48-volt DC input), and such PSUs may comprise a DC-DC converter for converting voltage to a desired level.
In traditional approaches, a PSU may be capable of, immediately after removal of the AC source to the PSU, providing electrical energy at its output for a period of time using the stored charge on the bulk capacitor to provide an output DC voltage. Such a period of time is limited, of course, as once the AC input is not available, the bulk capacitor will discharge and the PSU will shut down.
In response to an impending shutdown resulting from loss of AC input to a PSU, a write-back cache may attempt to flush data to a non-volatile memory, and the hold-up time of the bulk capacitor may provide sufficient time for the write-back cache to use available electrical energy from the PSU in order to complete the cache flush before the PSU ceases generating an output voltage as a result of the withdrawal of the input alternating-current waveform. It is noted that in some information handling systems, instead of an AC input source, a DC input source may be used. In such instances, similar hold-up time mechanisms may be provided.
Non-volatile memory is often implemented in memory modules called non-volatile dual-inline memory modules (NVDIMMs), and NVDIMMs may be any of the following types: NVDIMM-N, NVDIMM-F, or NVDIMM-P. These memories bring persistence to the memory channel and can be used in a variety of modes: as a volatile memory, as a load-store byte addressable memory, or as a block device. While NVDIMM-N is implemented using a volatile memory (e.g., dynamic random access memory or DRAM) upon which a save operation is performed in response to a power failure to transfer data of the volatile memory to non-volatile memory for later recovery, NVDIMM-F and NVDIMM-P devices are non-DRAM based true storage class memories (SCMs) as they offer larger capacities and can be used as storage devices residing on the memory channel.
DRAM-based NVDIMM-N devices have predictable read/write latencies. In other words, a host memory controller may orchestrate an entire sequence of events, as the controller knows when to send write data and when to receive read data. However, with NVDIMM-F and NVDIMM-P devices, reads and writes are non-deterministic in nature, as these modules may have an on-DIMM controller that assists in the data transfer to and from the media. The data transfer on the DIMM typically takes place between a front-end buffer and the media. The number of entries in the front-end buffer act as credits, and there is flow control between the host and the on-DIMM controller. The host decrements the available credit every time a write transaction is sent, and increments the credit when a response on completion of the write operation is received from the DIMM module. Similarly, for reads, the host controller maintains a number of available credits and associates every read command with a specific identifier. The NVDIMM then responds back with the read identifiers for which the data is available, and then the host acknowledges this and prepares for the read data transfer. Such a split-transaction protocol allows out-of-order completion of reads. One of the reasons for the out-of-order completion of reads is because of finite endurance levels of SCMs and the need for wear-leveling on the media regions subject to wear.
Deterministic latencies with NVDIMM-N modules render it fairly simple to estimate a worst-case time needed to flush out the cache-data during an asynchronous DRAM refresh (ADR) operation. An ADR operation may be triggered whenever an information handling system detects an impending power failure, thereby necessitating the flow of data meant for the NVDIMMs caches on a processor. With NVDIMM-N, due to the predictable latencies, it is conceivable to get the worst case scenario if all the cache data were targeted to one NVDIMM-N. However, it becomes a significantly complicated task with other NVDIMM types, not only due to their larger foot-print (e.g., size in gigabytes), but also their unpredictable (e.g., longer) latencies.
For example, the level 3 cache typically present in a server processor is several tens of megabytes in capacity, and the worst case would be if the entire data for the level 3 is mapped to a specific NVDIMM module. These deterministic latencies at least allow a system architect to calculate the amount of time needed to flush the cache data in the best and worst case scenarios, and decide on the power supply requirements as the power supply is withdrawn. Thus, because the latencies are deterministic in nature, supporting an entire flush by a PSU for NVDIMM-N may be feasible.
However, such calculations and determination are not as simple with other NVDIMM types (NVDIMM-P and NVDIMM-F types), due to the non-deterministic latencies associated with these memories, as explained above. Providing power by taking the absolute worst case scenario (taking wear-leveling like latencies for every write) may not be feasible, because the read/write latencies are non-deterministic in nature, and to this there is an implicit flow-control between the memory controller and the DIMMs. Accordingly, more efficient system architectural approaches are necessary to address the cache data flush to SCM memory modules during cache flushing and ADR operation.